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AI inference: size memory before counting GPUs

An AI service can load a model successfully and still become frustratingly slow when customers arrive.

3 min read · Reviewed
AI inference: size memory before counting GPUs
Original AI-created conceptual illustration · BLACK ROCK Academy

Long conversations consume memory, requests queue and data has to reach the accelerators. The purchasing conversation becomes clearer once the workload has a name and a measurable target.

Start with the requests users will send

Specify context length, concurrent requests, first-token latency and output tokens per second. A seven-billion-parameter model stored at two bytes per parameter requires about 14 GB of decimal weight storage alone. Runtime buffers, activations, allocator overhead and the KV cache are additional. Quantization changes the weight budget but needs application-level quality checks; a smaller file is not proof of unchanged accuracy or faster end-to-end service.

Where the memory goes

For an illustrative attention configuration, KV bytes ≈ 2 × layers × KV heads × head dimension × bytes × tokens × batch. With 32 layers, 8 KV heads, dimension 128, two-byte values, 8,192 tokens and batch 8, the result is 8 GiB. This assumes the stated architecture and cache layout; it is not a universal model requirement. Admission control must account for growing sequences, cancellation and memory fragmentation, not merely successful model loading.

Keeping accelerators supplied with data

Separate compute, storage and management traffic according to workload and failure domains. Increasing GPU count can increase communication demands and leave expensive accelerators waiting for input. Measure prefill and decode separately, then test realistic request distributions, including long prompts.

Record p95/p99 latency, tokens per joule, saturation and recovery. Compare single-node and distributed serving with the same quality and latency target. The engineering decision is the smallest system meeting that target with operating headroom, not the largest advertised accelerator total.

Sources

  1. NVIDIA — TensorRT KV cache ↗
  2. NVIDIA — DGX SuperPOD architecture ↗

Reviewed: 2026-10-07

ADNET / Data centre interconnection

A decision for regional networks

The network brief should follow the serving plan: where data is stored, which nodes communicate and how much delay the application can tolerate. These choices give a data-centre interconnection its purpose.

Explore solution ↗

Adapted for ADNET from the author's Black Rock Academy essay. Original technical discussion and references are retained; the ADNET application note below adds the corridor-planning context.

Read the original essay ↗

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Hamid Reza Assariha. AI inference: size memory before counting GPUs. ADNET, 2026-10-09. https://www.adnetinternet.com/insights/gpu-ai-inference-memory-network/

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